Top electrode in a strongly oxidizing environment

ABSTRACT

An improved charge storing device and methods for providing the same, the charge storing device comprising a conductor-insulator-conductor (CIC) sandwich. The CIC sandwich comprises a first conducting layer deposited on a semiconductor integrated circuit. The CIC sandwich further comprises a first insulating layer deposited over the first conducting layer in a flush manner. The first insulating layer comprises a structure having a plurality of oxygen cites and a plurality of oxygen atoms that partially fill the oxygen cites, wherein the unfilled oxygen cites define a concentration of oxygen vacancies. The CIC sandwich further comprises a second conducting layer deposited over the first insulating layer in a strongly oxidizing ambient so as to reduce the concentration of oxygen vacancies in the first insulating layer, so as to provide an oxygen-rich interface layer between the first insulating layer and the second conducting layer, and so as to trap a plurality of oxygen atoms within the second conducting layer. The oxygen-rich interface layer and second conducting layer act as oxygen vacancy sinks for absorbing migrating oxygen vacancies that originate from the first insulating layer to thereby reduce the concentration of oxygen vacancies in the first insulating layer and to thereby reduce the buildup of oxygen vacancies at the interface layer. Thus, the first insulating layer provides an increased dielectric constant and an increased resistance to current flowing therethrough so as to increase the capacitance of the CIC sandwich and so as to reduce leakage currents flowing through the CIC sandwich.

RELATED APPLICATIONS

This is a continuation application of U.S. Application Ser. No.10/039,215 filed Jan. 3, 2002 which was a divisional of U.S. applicationSer. No. 09/652,863, filed Aug. 31, 2000, now U.S. Pat. No. 6,682,969which are hereby incorporated by reference in their entirety herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to semiconductor integratedcircuits and, in particular, relates to oxide dielectric materialshaving reduced oxygen vacancies and methods for providing the same.

2. Description of the Related Art

Dielectric materials are extensively relied upon by the semiconductorindustry to form charge storing circuit elements within integratedcircuits. For example, a typical capacitor structure within anintegrated circuit comprises an insulating dielectric layer sandwichedbetween a lower and upper conducting electrode. This provides thecapacitor structure with a desired capacitance, C, that variesproportionally with the dielectric constant, k, of the dielectric layerand the area, A, of the electrodes. Furthermore, some types of memorydevices, such as Dynamic Random Access Memory (DRAM) devices, comprise aplurality of these capacitor structures such that the continued presenceor absence of a detectable charge on a single capacitor structureindicates the state of a single memory cell of the memory device.

However, due to the limitations of known manufacturing methods, thetypical dielectric layer often suffers from a substantially largeconcentration of oxygen vacancy defects. In particular, an oxygenvacancy exists whenever the crystal structure of an oxide dielectric ismissing an oxygen atom. Unfortunately, the presence of oxygen vacancieswithin the dielectric causes the dielectric layer to have a decreaseddielectric constant as well as a decreased electrical resistance.

Thus, a capacitor structure formed of such a dielectric layer usuallyprovides a decreased capacitance, thereby reducing the charge depositedon the electrodes of the capacitor structure in response to a specificvoltage differential applied across it electrodes. Moreover, sincerelatively large leakage currents flow through the dielectric layer ofthe capacitor structure, the capacitor structures discharges in arelatively short period of time. Consequently, when used in DRAMdevices, such capacitor structures require a relatively high refreshrate and, therefore, lengthen the time required to access data from suchdevices.

Unfortunately, the problems associated with oxygen vacancies withindielectric materials are becoming more apparent as integrated circuitsare formed with increasingly smaller circuit elements. For example, highdensity DRAM devices requiring a large number of capacitor structuresdemand the electrodes of each capacitor structure to have a relativelysmall area. Thus, in order to provide a sufficient capacitance inresponse to the reduced area, A, of the electrodes, dielectric materialshaving a relatively large dielectric constant, k, otherwise known ashigh-k dielectric materials, are required. However, known high-kdielectric materials, such as tantalum pentoxide (Ta2O5), bariumstrontium titanate (BST), barium titanate (BT) lead zirconium titanate(PZT), and strontium bismuth tantalate (SBT), require the presence ofoxygen atoms throughout their crystal structures. Furthermore, thedielectric constant and the electrical resistance of these high-kmaterials are especially sensitive to the presence of oxygen vacancies.Thus, these capacitor structures are more likely to be formed with aninsufficient capacitance for developing a detectable charge as well asan insufficient resistance for maintaining the detectable charge.

To address the problem of oxygen vacancies in dielectric materials,manufacturers often subject DRAM integrated circuits to re-oxidationanneals. For example, DRAM integrated circuits are usually exposed to afirst annealing process which heats the integrated circuit in anoxidizing environment subsequent to the deposition of the dielectricmaterial and prior to the deposition of the upper electrode so as tosource oxygen atoms to the exposed dielectric material to thereby reducethe concentration of oxygen deficiencies. However, since the oxygendeficiencies are often deeply positioned within the oxide dielectriclayer, a relatively large concentration of oxygen deficiencies remain.Furthermore, during the deposition of the upper electrode layer, asubstantial portion of the remaining oxygen deficiencies are often drawntoward the upper electrode which often forms an oxygen deficiency-richinterface layer inbetween the dielectric layer and the upper electrode.Unfortunately, the formation of this defective interface layer causesthe capacitor structure to suffer from a disproportionately smalldielectric constant as well as a disproportionately small resistance toleakage current.

In an effort to repair the defective interface layer between thedielectric layer and the upper electrode layer, manufacturers oftensubject DRAM integrated circuits to a second re-oxidation annealingprocess in an oxidizing environment subsequent to the deposition of theupper electrode. However, the upper electrode essentially acts as abarrier which inhibits oxygen atoms from diffusing into the underlyingdielectric layer. Thus, the effectiveness of the second annealingprocess is substantially limited.

From the foregoing, therefore, it will be appreciated that there is aneed for an improved capacitor structure formed in an integratedcircuit. In particular, there is a need for the capacitor structure toinclude a dielectric material with a reduced concentration of oxygendeficiencies. Furthermore, there is a need for the capacitor structureto have a reduced buildup of oxygen deficiencies at an interface layerbetween the dielectric material and an upper electrode layer of thecapacitor structure. To this end, there is a need for an improved methodof depositing the upper electrode above the dielectric material so as toreduce the concentration of oxygen deficiencies throughout thedielectric material.

SUMMARY OF THE INVENTION

The aforementioned needs are satisfied by the preferred embodiments ofthe improved conductor-insulator-conductor (CIC) sandwich of the presentinvention. In one embodiment, a method of forming an improved CICsandwich for an integrated circuit is provided. In particular, themethod comprises depositing a first conducting layer on the integratedcircuit. The method further comprises depositing a first insulatinglayer in contact with the first conducting layer, wherein the firstinsulating layer comprises a plurality of oxygen atoms in a structuredefining a first concentration of oxygen vacancies. The method furthercomprises depositing a second conducting layer in contact with the firstinsulating layer in a strongly oxidizing ambient so as to reduce theconcentration of oxygen vacancies in the first insulating layer from thefirst concentration, wherein reducing the concentration of oxygenvacancies in the first insulating layer provides the first insulatinglayer with improved electrical characteristics.

In another embodiment, a method of forming a memory cell for a DRAMintegrated circuit having an improved CIC sandwich is provided. Inparticular, the method comprises forming a first transistor gate on asubstrate, depositing a first insulating layer over the first transistorgate, and forming a conductive plug that extends from an active regionof the first transistor gate through the first insulating layer. Themethod further comprises forming a structural layer over the firstinsulating layer, and forming a via that extends into the structurallayer so as to expose the conductive plug. The method further comprisesdepositing a first conducting layer over the structural layer so as tocoat the interior surfaces of the via with the first conducting layerand so as to electrically couple the conductive plug with the firstconducting layer. The method further comprises depositing a secondinsulating layer over the first conducting layer, wherein the secondinsulating layer comprises a plurality of oxygen atoms in a structuredefining a first concentration of oxygen vacancies. The method furthercomprises depositing a second conducting layer over the secondinsulating layer in a strongly oxidizing ambient so as to source oxygenatoms to the second insulating layer so that the concentration of oxygenvacancies of the second insulating layer is reduced from the firstconcentration.

In another embodiment, the aforementioned needs are satisfied by anintegrated circuit comprising an improved conductor-insulator-conductor(CIC) sandwich. In particular, the CIC sandwich comprises a firstconducting layer deposited over the integrated circuit. The CIC sandwichfurther comprises a first insulating layer deposited over the firstconducting layer, wherein the first insulating layer comprises astructure having a plurality of oxygen sites partially filled by aplurality of oxygen atoms. Furthermore, the unfilled oxygen sites definea concentration of oxygen vacancies. The CIC sandwich further comprisesa second conducting layer deposited over the first insulating layer. TheCIC sandwich further comprises an oxygen-rich interface layer interposedbetween the first insulating layer and the second conducting layer.Specifically, the oxygen-rich interface layer acts as a sink forabsorbing oxygen vacancies that migrate from the first insulating layerso as to reduce the buildup of oxygen vacancies at the interface layerand so as to reduce the concentration of oxygen vacancies of the firstinsulating layer.

From the foregoing, it should be apparent that preferred embodiments ofthe CIC sandwich and the methods for providing such enable the CICsandwich to have improved electrical characteristics. In particular, thereduced concentration of oxygen vacancies within the CIC sandwich enablethe CIC sandwich to have an increased dielectric constant as well as anincreased resistance to leakage current flowing through the CICsandwich. Thus, the preferred embodiments of the CIC sandwich of thepresent invention are more suitable for use in charge storing devicesthan CIC sandwiches known in the art. These and other objects andadvantages of the present invention will become more apparent from thefollowing description taken in conjunction with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-section of one embodiment of a partiallyfabricated memory cell;

FIG. 2 is a schematic cross-section of a conductor-insulator-conductorstructure of FIG. 1;

FIG. 3 is the schematic cross-section of FIG. 2 illustrating thepresence of oxygen vacancies and trapped oxygen atoms within theconductor-insulator-conductor structure; and

FIG. 4 is a schematic cross-section of the memory cell of FIG. 1 furtherincorporating the conductor-insulator-conductor structure of FIG. 2 withan overlying dielectric.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Reference will now be made to the drawings wherein like numerals referto like parts throughout. While illustrated in the context of a dynamicrandom access memory (DRAM) cell, embodiments of the invention can beused to improve a wide range of products and processes. For example, theinvention can be used to improve materials with high dielectricconstants, metal-oxide-semiconductor structures, metal-oxide-metalstructures and the like.

FIG. 1 illustrates a partially fabricated memory cell 4 formed withinand over a semiconductor substrate 10, in accordance with one embodimentof the present invention. While the illustrated substrate 10 comprisesan intrinsically doped monocrystalline silicon wafer, it will beunderstood by one of skill in the art of semiconductor fabrication thatthe “substrate” in other arrangements can comprise other forms ofsemiconductor layers which include active or operable portions ofsemiconductor devices.

A plurality of transistor gate electrodes 12 overlie the substrate 10,adjacent transistor active areas 14 within the substrate 10. It will beunderstood that several transistors are formed across a memory arraywithin a DRAM circuit or chip. Field oxide elements 16 isolate theactive areas 14 of different transistors. In the illustrated embodimentof FIG. 1, the field oxide elements 16 are formed using the well knownlocal oxidation of silicon process (LOCOS). However, it is to beunderstood that the field oxide elements 16 could be formed using otherprocesses such as shallow trench isolation (STI). In one embodiment, thewidth of the gates are preferably less than about 0.25 microns (μm).

In one embodiment, the field oxide elements 16 are formed using the wellknown LOCOS (Local Oxidation of Silicon) technique. However, in anotherembodiment, the field oxide elements 16 could be fabricated by anotherprocess, such as STI (Shallow Trench Isolation).

A first insulating layer 18 is shown covering the gate electrodes 12.Generally, this insulating layer 18 comprises a form of oxide, such asborophosphosilicate glass (BPSG). Depending upon the presence or absenceof other circuit elements, the first insulating layer 18 typically has athickness between about 0.15 μm to 1.5 μm. For example, certain DRAMcircuit designs call for “buried” digit lines running below the cellcapacitors, such that a thicker insulating layer is required toelectrically isolated the digit line from the underlying transistors andthe overlying capacitors.

A conductive contact 20 is shown extending through the first insulatinglayer 18 to electrically contact an active area 14 between gateelectrodes. In the illustrated embodiment, the material of the contact20 comprises conductively doped polycrystalline silicon or polysilicon,which advantageously can be deposited into deep, narrow contact viaswith good step coverage by chemical vapor deposition (CVD). Inaccordance with industry terminology, the conductive contact shall bereferred to as a “poly plug” 20. In another embodiment, the poly plug 20can include a variety of conductors including tungsten (W), aluminum(Al) or the like. As described in further detail below, the poly plug 20has a reduced level of oxidation that occurs when removing oxygenvacancies from the memory cell 4.

The barrier layer 32 advantageously acts as a diffusion barrier toreduce oxidation of the underlying poly plug 20. The barrier layer 32may comprise tantalum (Ta), tantalum nitride (TaN), tantalum siliconnitride (TaSiN), titanium nitride (TiN), titanium aluminum nitride(TiAlN), titanium silicon nitride (TiSiN), tungsten nitride (WN_(x)),tungsten silicon nitride (WSiN), silicon nitride (SiN), molybdenum (Mo)or the like. However, the skilled artisan will recognize that a widerange of materials can be used to form the barrier layer 32. The barrierlayer 32 can be formed by nitridizing a metallic film, such as Ta, Mo,Ti, and W, deposited on the poly plug 20 or by chemical vapor deposition(CVD), metal organic chemical vapor deposition (MOCVD), low temperaturesputtering or the like. In one embodiment, the barrier layer 32 isapproximately 10 angstroms (Å) to approximately 1000 or more angstroms(Å) thick. In certain other embodiments, the barrier layer 32 is notused.

A structural layer 22 is then formed over the first insulating layer 18and the barrier layer 32. As will be better understood from the methodsdescribed below, this structural layer 22 need not become a permanentpart of the circuit. Accordingly, the skilled artisan has a great dealof flexibility in the selection of this material. Preferably, thestructural layer 22 is selectively etchable relative to the underlyingfirst insulating layer 18. In one embodiment, the structural layer 22 isBPSG. The surface area and thus the capacitance of the memory cell 4 isinfluenced by the thickness of the structural layer 22. For theillustrated circuit, using 0.25 μm resolution, the structural layer 22preferably has a thickness of greater than about 0.4 μm, more preferablybetween about 0.4 μm and 2.0 μm.

A via 24 is formed in the structural layer 22 to expose the underlyingpoly plug 20, and a conductive layer 26 is deposited over the structurallayer 22 and into the via 24 to coat the inner surfaces of the via 24and to make electrical contact with the poly plug 20. The top of thestructural layer 22, and the portion of the conductive layer 26overlying the structural layer 22, can then be planarized to leave theconductive layer 26 isolated within the via 24, as shown in FIG. 1. Suchplanarization can be accomplished by mechanical abrasion, preferablychemically aided by etchants in a slurry in a chemical mechanicalplanarization or polishing (CMP) process.

The conductive layer 26 serves as a bottom electrode of the memory cell4, and can comprise a conductively doped polysilicon, hemisphericalgrain (HSG) polysilicon, platinum (Pt), ruthenium (Ru), ruthenium oxide(RuO_(x)), iridium (Ir), iridium oxide (IrO_(x)), palladium (Pd),tungsten (W) tungsten nitride (WN_(x)), tantalum nitride (TaN), titaniumnitride (TiN), titanium oxygen nitride (TiON) or the like. Theillustrated conductive layer 26 thus takes on a three-dimensionalfolding shape that is of greater surface area than the area of thesubstrate 10 which the memory cell 4 occupies. Other methods ofincreasing surface area can include creating a rough surface on theconductive layer 26, creating multiple concentric container shapes forone memory cell, and creating a bottom electrode stud. The skilledartisan will find application for the processes and materials discussedbelow for any of a number of capacitor configurations.

The conductive layer 26 can be deposited by chemical vapor deposition(CVD), Low Pressure Chemical Vapor Deposition (LPCVD), metal organicchemical vapor deposition (MOCVD), plasma enhanced chemical vapordeposition (PECVD), physical vapor deposition (PVD), electroplating, orthe like. While the thickness of the conductive layer 26 isapproximately 100 angstroms (Å) to approximately 1000 (Å), the skilledartisan will recognize that the thickness of the conductive layer 26 canvary over a wide variety of ranges.

As shown in FIG. 1, the memory cell 4 further comprises an insulatinglayer 34 which is deposited above the conductive layer 26 and above thestructural layer 22. As will be described in greater detail below inconnection with FIGS. 2 through 4, the insulating layer 34 forms a partof a conductor—insulator—conductor (CIC) structure 30 of the memory cell4.

The insulating layer 34 is an insulator that provides electricalinsulation. In one embodiment of the invention, the insulating layer 34is a conventional dielectric material such as silicon nitride. Inanother embodiment, the insulating layer 34 is a material with a highdielectric constant. Materials having high dielectric constants greaterthan 9 are to be distinguished from conventional dielectric materialssuch as silicon nitride which has a dielectric constant of approximately7. The high constant dielectric materials typically comprise inorganicnon-metallic oxides such as aluminum oxide (Al₂O₃), tantalum pentoxide(Ta₂O₅), oxide paraelectric materials, and ferroelectric materials,including by way of example, barium strontium titanate ((BaSr)TiO₃ orBST), strontium titanate (ST), barium titanate (BT), lead zirconiumtitanate (PZT), strontium bismuth tantalate (SBT), or the like.

In the preferred embodiments, the insulating layer 34 comprises materialin a crystalline state. However, it will be appreciated that theinsulating layer 34 could comprise material in a non-crystalline state.For example, in one embodiment, the insulating layer 34 could comprisean amorphous dielectric material.

In one embodiment, the dielectric 34 is deposited by alternating current(AC) sputtering at a temperature range of approximately 50° C. toapproximately 700° C. A target material can comprise a stoichiometriccomposition of powdered materials. The thickness of such a dielectriclayer is preferably in the range of approximately 20 Å to approximately500 Å thick. Other deposition techniques such as CVD, LPCVD, PECVD orMOCVD can be utilized. For example, in one embodiment, the dielectric 34comprises tantalum pentoxide and is between approximately 40 Å andapproximately 120 Å thick. Preferably, the tantalum pentoxide isapproximately 70 Å thick. The dielectric constant (k) of tantalumpentoxide is 25 to 50, and when doped with silicon can increase up to130. As is known in the art, tantalum pentoxide can be formed bychemical vapor deposition, using an organometallic precursor.

In another embodiment, the dielectric 34 comprises barium strontiumtitanate that is between approximately 100 Å and approximately 500 Åthick. Preferably, the barium strontium titanate is approximately 200 Åto approximately 300 Å thick. While the dielectric constant (k) of thebarium strontium titanate varies from about 100 to 600, depending uponthe phase and thickness of the material, the preferred dielectric 34 hasa dielectric constant of about 300. As is known in the art, bariumstrontium titanate is preferably deposited by chemical vapor depositiontechniques comprising reacting volatile complexes containing barium(Ba), strontium (Sr) and titanium (Ti) in an oxygen ambient.

FIG. 2 illustrates the conductor-insulator-conductor (CIC) structure 30of the memory cell 4 of FIG. 1. The CIC 30 comprises the conductivelayer 26, the dielectric 34, and the second conductive layer 36. Theconductive layer 26 is hereinafter referred to as the bottom electrode26 and the conductive layer 36 is hereinafter referred to as the upperelectrode 36.

During the deposition of the dielectric 34, a plurality of oxygenvacancies 40 often develop wherein oxygen atoms are missing at varioussites throughout the dielectric 34. For example, the dielectric 34comprising tantalum pentoxide or barium strontium titanate may containdefects where missing oxygen atoms deform their crystalline structuresand yield poor dielectric properties such as lower dielectric constantsand higher leakage currents. As will be explained in more detail below,one embodiment of the invention reduces the oxygen vacancies in thedielectric 34 by exposing the CIC 30 to a strongly oxidizing ambienthaving an increased concentration of oxygen atoms 37 while the secondconductive layer 36 is deposited above the dielectric 34.

After depositing the dielectric 34, the upper electrode 36 is depositedover the dielectric 34. The upper electrode 36 typically comprisesplatinum (Pt), ruthenium (Ru), ruthenium oxide (RuO_(x)), iridium (Ir),iridium oxide (IrO_(x)), palladium (Pd), tungsten (W), tungsten nitride(WN), tantalum nitride (TaN), titanium nitride (TiN), titanium oxygennitride (TiON), or the like. A suitable deposition process issputtering, CVD, LPCVD, PECVD, MOCVD or the like. The upper electrode 36is preferably deposited to a thickness range of approximately 100Å toapproximately 2000 Å.

In prior art devices, an electrode is typically deposited in an ambienthaving only enough oxygen to provide the electrode with a stablestoichiometry. For example, if the electrode is formed of IrO_(x), theoxygen concentration is typically chosen so that stoichemetricallystable IrO₂ is formed. However, to decrease the concentration of oxygenvacancies 40 in the dielectric 34, the upper electrode 36 of thepreferred embodiment of the present invention is deposited over thedielectric 34 in the strongly oxidizing ambient 35. As a result, theupper electrode 36 is highly oxidized such that the quantity of oxygenatoms within the upper electrode is greater than that which is requiredfor stoicheometric stability. For example, in one embodiment, the upperelectrode 36 is formed of IrO_(x) wherein x is greater than 2.0 and lessthan 2.5 such that the electrical properties of the upper electrode 36are not substantially affected by the excess oxygen atoms.

It will be appreciated that depositing the upper electrode 36 in thestrongly oxidizing ambient 35 provides many advantages as will now bedescribed in connection with FIG. 3. In particular, since the dielectric34 is initially exposed to the ambient 35 and since the ambient 35comprises the relatively high concentration of oxygen atoms 37, arelatively large number of oxygen atoms immediately diffuse into thedielectric 34. Thus, a relatively large number of oxygen atoms from theambient 35 combine with the oxygen vacancies 40 in the dielectric 34 soas to provide a reduced concentration of oxygen vacancies 40 in thedielectric 34. Accordingly, the reduced concentration of oxygenvacancies 40 in the dielectric 34 provide the CIC 30 with increasedcapacitance and decreased leakage currents.

Another advantage provided by depositing the upper electrode 36 in thestrongly oxidizing ambient 35 is the formation of an oxygen-richinterface layer 42 between the dielectric 34 and the upper electrode 36.In particular, early in the process of depositing the upper electrode36, a relatively large number of oxygen atoms 37 from the stronglyoxidizing ambient 35 engage with the exposed surface of the dielectric34 and are subsequently trapped by the overlying upper electrode 36 soas to form the layer 42 which acts as an oxygen vacancy sink.Consequently, in the event that some of the oxygen vacancies 40 of thedielectric layer 34 migrate toward the interface layer 42, the migratingoxygen vacancies 40 will likely combine with the oxygen of the interfacelayer 42. This results in a substantial cancellation of the migratingvacancies 40 and, thus, reduces the likelihood that the migrating oxygenvacancies 40 will accumulate at the interface layer 42. Accordingly,since crystalline defects at the interface layer 42 are largely due tothe buildup of oxygen vacancies, the reduced buildup of oxygen vacanciesprovides increased capacitance and decreased leakage resistance. Yetanother advantage provided by depositing the upper electrode 36 in thestrongly oxidizing ambient 35 is the trapping of oxygen atoms at aplurality of oxygen-rich regions 44 throughout the upper electrode 36.In particular, the trapped oxygen atoms of the regions 44 in the upperelectrode 36 provide an increased capacity for absorbing oxygenvacancies that migrate into the upper electrode 36. Thus, since theseoxygen vacancies are no longer able to migrate back toward thedielectric 34, the trapped oxygen atoms of the regions 44 of the upperelectrode 36 assist in further providing the CIC 30 with an increasedcapacitance and an increased resistance to leakage currents.

Still yet another advantage provided by depositing the upper electrode36 in the strongly oxidizing ambient 35 is that of reduced manufacturingtime. In particular, since depositing the upper electrode 36 in thestrongly oxidizing ambient 35 provides the CIC 30 with the reducedconcentration of oxygen vacancies 40, the need for conventionalannealing processes designed to reduce the oxygen vacancies 40 isreduced. Thus, in embodiments that do not utilize an annealing processto further reduce the concentration of oxygen vacancies 40, the memorycell 4 can be manufactured in less time.

With reference now to FIG. 4, the memory cell 4 is shown with thecompleted capacitor structure 30. A third conductive layer 38 may existabove the upper electrode 36. Preferably the third conductive layer 38forms a part of the top electrode 36. Exemplary materials for the thirdconductive layer 38 include polysilicon, tungsten, tungsten nitride(WN_(x)), and titanium nitride (TiN).

An interlevel dielectric (ILD) 41 has also been formed over the upperelectrode 36. Typically, the ILD 41 comprises a form of oxide, such asborophosphosilicate glass (BPSG). Deposition of the BPSG may be followedby a reflow anneal step for better step coverage and avoiding keyholes,as well as to densify the layer. The reflow is conducted by heating thewafer to temperatures of approximately 550° C. to 900° C. If notseparately annealed before this point, the deposited amorphousdielectric 34 can be converted to a crystalline phase during this hightemperature reflow. Although not shown, the skilled artisan willappreciate that contacts are created through the BPSG 41 to connect thetop electrode 36, 38 to wiring formed above or within the BPSG 41.

To enhance the removal of the oxygen vacancies 40 from the dielectriclayer 34, it will be appreciated that the CIC 30 could be exposed to anadditional processing step whereby the oxygen vacancies 38 are inducedto migrate toward the interface layer 42 (FIG. 3). In particular, in oneembodiment, the memory cell 4 is exposed to an electric field in a wellknown manner that urges a portion of the remaining oxygen vacancies 40in the dielectric layer 34 to migrate toward the interface layer 42.Accordingly, the oxygen-rich interface layer 42 subsequently absorbs thedisplaced oxygen vacancies, thereby preventing the buildup of oxygenvacancies at the interface layer 42 and further reducing theconcentration of oxygen vacancies 38 within the dielectric 34.

Thus, it will be appreciated that the preferred embodiments of the CIC30 of the present invention provide improved capacitance and reducedleakage currents. Such improvements are realized by exposing thedielectric 34 of the CIC 30 to the strongly oxidizing ambient 35 duringthe deposition process of the upper electrode 36. This reduces theconcentration of oxygen vacancies 40 of the dielectric 34 to therebyincrease the dielectric constant and the resistance of the dielectric34.

Although the preferred embodiment of the present invention has shown,described and pointed out the fundamental novel features of theinvention as applied to this embodiment, it will be understood thatvarious omissions, substitutions and changes in the form of the detailof the device illustrated may be made by those skilled in the artwithout departing from the spirit of the present invention.Consequently, the scope of the invention should not be limited to theforegoing description, but should be defined by the appending claims.

1. An integrated circuit comprising an improved conductor-insulator-conductor (CIC) sandwich, wherein the CIC sandwich comprises: a first conducting layer; a first insulating layer deposited over the first conducting layer, wherein the first insulating layer comprises a structure having a plurality of oxygen cites partially filled by a plurality of oxygen atoms, wherein the unfilled oxygen cites define a concentration of oxygen vacancies; a second conducting layer deposited over the first insulating layer; and an oxygen-rich interface layer interposed between the first insulating layer and the second conducting layer, wherein the oxygen-rich interface layer acts as a sink for absorbing oxygen vacancies that migrate from the first insulating layer so as to reduce the buildup of oxygen vacancies at the interface layer and so as to reduce the concentration of oxygen vacancies of the first insulating layer. 